A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.

A semiconductor die includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads that include a first die bond pad exposed by a passivation layer, a top dielectric layer over the passivation layer, and a metal layer electrically connected to the first die bond pad. A pillar is on the metal layer over the first die bond pad, and a solder cap is on a top side of the pillar. The solder cap includes an essentially vertical sidewall portion generally beginning at a top corner edge of the pillar.

An arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a donor chuck; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-controlled compression rod so as to bond the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate so as to form an integrated circuit assembly.

A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.