A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.

The present invention comprises an arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a first or a second donor chuck respectively; monitoring the solder ball and chip arrangement by a computer-controlled camera; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, the monitored by a second computer controlled camera; flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate, monitored and positionally controlled by a third computer-controlled camera; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-controlled compression rod so as to bond the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate so as to form an integrated circuit assembly.

A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.

The present invention provides a ball placement structure and a preparation process thereof. The ball placement structure includes a substrate, a conductive layer, a passivation layer, a seed layer, and a metal layer which are stacked in sequence, wherein a plurality of solder balls is respectively placed onto the metal layer, and a retaining wall is disposed between any adjacent solder balls, and is configured to prevent bridging between the solder balls.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises forming a first-stage assembly, including: align and fix at least one first-stage device to a target position on a carrier plate by utilizing the self-alignment capability of first-stage alignment solder joints; and while using a clamping board to support an exposed side of the at least one first-stage device, performing injection molding through an opening in the carrier board or the clamping board. The packaging method further comprises align and fix a second-stage device to a target position on the first-stage assembly by utilizing the self-alignment capability of second-level alignment solder joints between the first-stage assembly and the second-stage device. The packaging method improves the operation speed and accuracy of the picking and placing of the first-stage device and the second-stage device, resulting in improved process efficiency and reduced process cost.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device, a carrier board, and a clamping board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; and injecting a molding compound through one or more openings in one or both of the carrier board and the clamping board to form a molded package body encapsulating the at least one semiconductor device between the carrier board and the clamping board attached to the active surface of the at least one semiconductor device.

An electronic assembly and methods of making the assembly are disclosed. The electronic assembly includes a substrate with an elastic member having an intrinsic stress profile. The elastic member has an anchor portion on the surface of the substrate; and a free end biased away from the substrate via the intrinsic stress profile to form an out of plane structure. The substrate includes one or more spacers on the substrate. The electronic assembly includes a chip comprising contact pads. The out of plane structure on the substrate touches corresponding contact pads on the chip, and the spacers on the substrate touch the chip forming a gap between the substrate and the chip.

A unitary wafer assembly arrangement for the application of solder balls onto a substrate for subsequent use in the electronics industry. This wafer tool assembly comprises a number of modules connected to one another and all serviced by a robotic arm to transfer processed wafers from one module to another. The tool assembly comprises a load port and pre-aligner module, a binder module, a solder ball mount module and a reflow module. A wafer inspection and repair module arrangement is also part of the tool assembly.