Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

A packaging structure and a formation method thereof are provided. The packaging structure includes a carrier board, and a plurality of semiconductor chips adhered to the carrier board. Each semiconductor chip has a functional surface and a non-functional surface opposite to the functional surface, and a plurality of pads are formed on the functional surface of a semiconductor chip of the plurality of chips. A metal bump is formed on a surface of a pad of the plurality of pads, and a first encapsulation layer is formed on the functional surface. The packaging structure also includes a second encapsulation layer formed over the carrier board.

Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.

A circuit module includes a flat substrate, a frame substrate, a first electronic component, and a first sealing member. First connection electrodes are disposed at a peripheral portion of one main surface of the flat substrate. Second connection electrodes are disposed on one main surface of the frame substrate at locations corresponding to the first connection electrodes. Each of the first connection electrodes and a corresponding one of the second connection electrodes are connected to each other via a first connection member. The first electronic component is sealed by the first sealing member. The first electronic component and the first sealing member are disposed in a cavity defined by the one main surface of the flat substrate and an inner surface of the frame substrate. The first sealing member is separated from the inner surface of the frame substrate.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.