Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

A circuit module includes a flat substrate, a frame substrate, a first electronic component, and a first sealing member. First connection electrodes are disposed at a peripheral portion of one main surface of the flat substrate. Second connection electrodes are disposed on one main surface of the frame substrate at locations corresponding to the first connection electrodes. Each of the first connection electrodes and a corresponding one of the second connection electrodes are connected to each other via a first connection member. The first electronic component is sealed by the first sealing member. The first electronic component and the first sealing member are disposed in a cavity defined by the one main surface of the flat substrate and an inner surface of the frame substrate. The first sealing member is separated from the inner surface of the frame substrate.

A protective tape that improves solder bonding properties and reduces wafer warping. The protective tape includes, in the following order, an adhesive agent layer, a first thermoplastic resin layer, a second thermoplastic resin layer, and a matrix film layer. The protective tape satisfies the conditions expressed by the following formulae (1) to (3):
Ga>Gb(1)
Ta<Tb(2)
(Ga*Ta+Gb*Tb)/(Ta+Tb)1.4E+06 Pa.(3)
Ga represents a shear storage modulus of the first thermoplastic resin layer at a pasting temperature at which the protective tape is pasted; Gb represents a shear storage modulus of the second thermoplastic resin layer at the pasting temperature at which the protective tape is pasted; Ta represents a thickness of the first thermoplastic resin layer; and Tb represents a thickness of the second thermoplastic resin layer.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.

Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.