H01L2224/11009

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Semiconductor Device and Method
20180158789 · 2018-06-07 ·

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

PROTECTIVE TAPE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

A protective tape that improves solder bonding properties and reduces wafer warping. The protective tape includes, in the following order, an adhesive agent layer, a first thermoplastic resin layer, a second thermoplastic resin layer, and a matrix film layer. The protective tape satisfies the conditions expressed by the following formulae (1) to (3):


Ga>Gb(1)


Ta<Tb(2)


(Ga*Ta+Gb*Tb)/(Ta+Tb)1.4E+06 Pa.(3)

Ga represents a shear storage modulus of the first thermoplastic resin layer at a pasting temperature at which the protective tape is pasted; Gb represents a shear storage modulus of the second thermoplastic resin layer at the pasting temperature at which the protective tape is pasted; Ta represents a thickness of the first thermoplastic resin layer; and Tb represents a thickness of the second thermoplastic resin layer.

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER

A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

METAL BONDING PADS FOR PACKAGING APPLICATIONS
20180061804 · 2018-03-01 ·

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

METAL BONDING PADS FOR PACKAGING APPLICATIONS
20180061804 · 2018-03-01 ·

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To improve the assemblability of a semiconductor device.

When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
20180040579 · 2018-02-08 ·

The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and are arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion.