Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

In semiconductor packaging technologies, a secondary packaging method of a TSV chip and a secondary package of a TSV chip are provided. The TSV chip has a forward surface and a counter surface that are opposite to each other, a BGA solder ball is disposed on the counter surface, and the secondary packaging method includes: placing at least one TSV chip on a base on which a stress relief film layer is laid; cladding the TSV chip via a softened molding compound; removing the base after the molding compound is cured, to obtain a secondary package of the TSV chip; and processing a surface of the secondary package to expose the BGA solder ball.

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.