In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode and made of a copper film, a solder ball electrode formed on the post electrode and made of ternary alloy containing tin, a terminal connected to the solder ball electrode and formed on a front surface of a wiring board, and a sealing material filling a gap between the semiconductor substrate and the wiring board. The post electrode includes a cylindrical stem portion and an overhanging portion positioned in an upper part of the stem portion and protruding to an outer side of the stem portion, the solder ball electrode is connected to an upper surface of the post electrode over the stem portion and the overhanging portion, and a sidewall of the stem portion contacts with the sealing material over the entire circumference thereof.

The present disclosure describes a structure with passivation layers with rounded corners and a method for forming such a structure. The method includes forming a first insulating layer on a substrate, where the substrate includes a first conductive structure. The method further includes forming an opening in the first insulating layer to expose the first conductive structure and forming a second conductive structure on the first insulating layer, where the second conductive structure is in contact with the first conductive structure through the opening. The method further includes removing a portion of the second conductive structure with a first etching condition, removing a portion of the first insulating layer with a second etching condition, different from the first etching condition, to form a rounded corner between a sidewall of the second conductive structure and a top surface of the first insulating layer, and depositing a second insulating layer on the first insulating layer and the second conductive structure.

A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.