An electronic package is provided. An electronic component and a plurality of conductive pillars electrically connected with the electronic component are embedded in an encapsulating layer. Each of the conductive pillars has a circumferential surface and two end surfaces wider than the circumferential surface in width. The encapsulating layer encapsulates and protects the electronic component effectively, so as to improve the reliability of the electronic package. A method for fabricating the electronic package is also provided.

A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

An electronic package is provided. An electronic component and a plurality of conductive pillars electrically connected with the electronic component are embedded in an encapsulating layer. Each of the conductive pillars has a circumferential surface and two end surfaces wider than the circumferential surface in width. The encapsulating layer encapsulates and protects the electronic component effectively, so as to improve the reliability of the electronic package. A method for fabricating the electronic package is also provided.

A solder ball includes 0.1% by mass or more and 10% by mass or less of In and a remainder of Sn. The ball has a yellowness (b*) in an L*a*b* color system of 2.8 or more and 15.0 or less and a lightness (L*) of 60 or more and 100 or less. The ball further includes at least one element selected from a group of 0% by mass or more and 4% by mass or less of Ag, 0% by mass or more and 1.0% by mass or less of Cu, 0% to 3% by mass in total of Bi and/or Sb, and 0% to 0.1% by mass in total of an element selected from a group of Ni, Co, Fe, Ge, and P, excluding a solder ball including 3% by mass of Ag, 0.5% by mass of Cu, 0.2% by mass of In and a remainder of Sn.

Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.

A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more apertures each of which is tapered from a top surface to a bottom surface thereof. The carrier is positioned beneath the bottom of the decal and includes cavities in a top surface. The cavities are located in alignment with the apertures of the decal. The decal is positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities. The feature cavities are shaped to receive one or more metal elements and are configured for receiving molten solder cooled in the cavities. The decal is separable from the carrier to partially expose metal core solder contacts. The receiving elements receive the metal core solder contacts thereon.

A solder ball includes 0.1% by mass or more and 10% by mass or less of In and a remainder of Sn. The ball has a yellowness (b*) in an L*a*b* color system of 2.8 or more and 15.0 or less and a lightness (L*) of 60 or more and 100 or less. The ball further includes at least one element selected from a group of 0% by mass or more and 4% by mass or less of Ag, 0% by mass or more and 1.0% by mass or less of Cu, 0% to 3% by mass in total of Bi and/or Sb, and 0% to 0.1% by mass in total of an element selected from a group of Ni, Co, Fe, Ge, and P, excluding a solder ball including 3% by mass of Ag, 0.5% by mass of Cu, 0.2% by mass of In and a remainder of Sn.

Circuit packages with a polymer layer around the bump interconnects have a reduced number of shorts between the bump interconnects and have reduced underfill delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects employed for passing logic signals, data signals, and/or power. The bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. The side surfaces of the bump interconnects extend in a direction from the second component to the first. The circuit package includes the polymer layer disposed on the surface of the first component around the bump interconnects and on the side surfaces of the bump interconnects. The polymer layer reduces shorts between the side surfaces of adjacent bump interconnects and reduces delamination of an underfill disposed between the first and second components.

An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 ?m on the cutting surface, an electrical conductivity of 11 to 101% IACS, and a Vickers hardness of 150 to 300 HV.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.