The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.

A semiconductor device includes a metal column that extends in a stretching direction; a polymer layer that surrounds the metal column from a direction crossing the stretching direction; and a guide that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture containing metal particles and polymers in a guide; and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column that stretches in a stretching direction of the guide from the metal particles.

A one-step water soluble (WS) flux process may reduce residue staining and increase yields for bond grid array (BGA) packages. In one example, the WS flux may use increased amounts of bonding polymer (BP) and reduced amounts of amine to increase viscosity. The increased viscosity may eliminate using a second no-clean flux and enable a single WS flux to both clean the associated substrate and provide stable solder ball support during reflow.

A one-step water soluble (WS) flux process may reduce residue staining and increase yields for bond grid array (BGA) packages. In one example, the WS flux may use increased amounts of bonding polymer (BP) and reduced amounts of amine to increase viscosity. The increased viscosity may eliminate using a second no-clean flux and enable a single WS flux to both clean the associated substrate and provide stable solder ball support during reflow.

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

The present disclosure relates to a production process for a solder electrode, including a step (1) of forming a coating film of a photosensitive resin composition on a substrate having an electrode pad; a step (2) of forming resist having an opening in a region corresponding to the electrode pad by selectively exposing the coating film to light and further developing the film; a step (3) of heating and/or exposing the resist to light; and a step (4) of filling the opening with molten solder while heating the solder. According to the production process for the solder electrode of the present disclosure, development of cracks on a resist surface can be prevented, and solder filling capability can be improved, even when the resist receives high heat during solder filling as in an IMS method, and therefore the solder electrode adapted for the purpose can be appropriately produced.

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

A method and apparatus for soldering a chip (1a) to a substrate (3). A chip carrier (8) is provided between a flash lamp (5) and the substrate (3). The chip (1a) is attached to the chip carrier (8) on a side of the chip carrier (8) facing the substrate (3). A solder material (2) is disposed between the chip (1a) and the substrate (3). The flash lamp (5) generates a light pulse (6) for heating the chip (1a). The heating of the chip (1a) causes the chip (1a) to be released from the chip carrier (8) towards the substrate (3). The solder material (2) is at least partially melted by contact with the heated chip (1a) for attaching the chip (1a) to the substrate (3).

A method and apparatus for soldering a chip (1a) to a substrate (3). A chip carrier (8) is provided between a flash lamp (5) and the substrate (3). The chip (1a) is attached to the chip carrier (8) on a side of the chip carrier (8) facing the substrate (3). A solder material (2) is disposed between the chip (1a) and the substrate (3). The flash lamp (5) generates a light pulse (6) for heating the chip (1a). The heating of the chip (1a) causes the chip (1a) to be released from the chip carrier (8) towards the substrate (3). The solder material (2) is at least partially melted by contact with the heated chip (1a) for attaching the chip (1a) to the substrate (3).