Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.

A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.