A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.

Disclosed are bump structures and bump structure fabrication methods. A bump structure including a pad and a bump on a top surface of the pad may be provided. The bump may include an upper bump portion and the lower bump portion, and the lower bump portion may include a pedestal portion in contact with the top surface of the pad and a pillar portion upwardly extending from the pedestal portion. A cross-sectional area of at least a portion of the pedestal portion along a first direction may be greater than a cross-sectional area of the pillar portion along the first direction.

Heat dissipation techniques include using metal features having one or more slanted or otherwise laterally-extending aspects. The metal features include, for example, tilted metal pillars, or metal bodies or fillets having an angled or sloping sidewall, or other metal features that extend both vertically and laterally. Such metal features increase the effective heat transfer area significantly by spreading heat in the in-plane (lateral) direction, in addition to the vertical direction. In some embodiments, slanted trenches are formed in photoresist/mold material deposited over a lower die, using photolithography and a multi-angle lens, or by laser drilling mold material deposited over the lower die. The trenches are then filled with metal. In other embodiments, metal features are printed on the lower die, and then molding material is deposited over the printed features. In any such cases, heat is conducted from a lower die to an upper die and/or an integrated heat spreader.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.

A semiconductor etch process is provided in which an undercut is minimized during an etch process through tight control of etch profile, recognition of etch completion, and minimization of over etch time to increase productivity.