The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes. The decrease in the bonding area also makes it possible to correspondingly improve the reproducibility of forming the diameter of the electrodes, and make reliable connection possible.

A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

A thin film element that includes a base material, a wiring conductor film disposed on the surface of the base material, a protective film that covers the surface of at least the wiring conductor film, an outer electrode, and a first resist film and a second resist film that cover the surface of the protective film. The protective film has a contact hole at a location overlapping the wiring conductor film. The outer electrode is disposed in the contact hole and on the surface of the wiring conductor film. The outer electrode is thicker than the protective film and has a side surface. The first resist film is in contact with the entire circumference of the side surface of the outer electrode, and the second resist film is disposed at a distance from the side surface of the outer electrode and the first resist film.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.