A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

A wiring substrate includes a resin insulating layer, a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer, a conductor pad formed on the resin insulating layer and connected to the via conductor, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post formed on the conductor pad and protruding from the coating insulating layer. The via conductor is formed such that the via conductor is increased in diameter toward the conductor pad, and the metal post is formed such that the metal post is increased in diameter toward the conductor pad.

A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.

Techniques for simultaneously plating features of varying sizes on a semiconductor substrate are provided. In one aspect, a method for electroplating includes: placing a shield over a wafer, offset from a surface of the wafer, which covers portions of the wafer and leaves other portions of the wafer uncovered; and depositing at least one metal onto the wafer by electroplating to simultaneously form metallurgical features of varying sizes on the wafer based on the shield altering local deposition rates for the portions of the wafer covered by the shield. An electroplating apparatus is also provided.

A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

In one instance, a semiconductor package includes a lead frame and a semiconductor die mounted to the lead frame via a plurality of bumps that are shaped or tapered. Each of the plurality of bumps includes a first end connected to the semiconductor die and an opposing, second end connected to the lead frame. The first end has an end surface area A1. The second end has an end surface area A2. The end surface area A1 of the first end is less than the end surface area A2 of the second end. Other aspects are disclosed.

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.