A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.

A serigraphy method for producing a soulder bump on the front surface of a substrate includes: forming a film on the front surface, forming an opening in the film, filling the opening with a souldering material, and removing the film. Forming a film on the front surface is preceded by the formation of an intermediate layer between the film and the front surface, the intermediate layer being adapted to exhibit a force of adherence at one and/or the other interface formed with the first front surface and the film lower than the force of adherence that can be formed between the film and the first front surface.

A light emitting diode (LED) element is provided. The LED element includes: an active layer configured to generate light; a first semiconductor layer disposed on a first surface of the active layer and doped with an n-type dopant; a second semiconductor layer disposed on a second surface of the active layer opposite to the first surface, the second semiconductor layer being doped with a p-type dopant; a first electrode pad and a second electrode pad electrically connected to the first semiconductor layer and the second semiconductor layer, respectively, the first electrode pad comprising a first contact surface and the second electrode pad comprising a second contact surface; and a conductive filler disposed on at least one contact surface from among the first contact surface and the second contact surface to increase a contact area of the at least one contact surface.

A light emitting diode (LED) element is provided. The LED element includes: an active layer configured to generate light; a first semiconductor layer disposed on a first surface of the active layer and doped with an n-type dopant; a second semiconductor layer disposed on a second surface of the active layer opposite to the first surface, the second semiconductor layer being doped with a p-type dopant; a first electrode pad and a second electrode pad electrically connected to the first semiconductor layer and the second semiconductor layer, respectively, the first electrode pad comprising a first contact surface and the second electrode pad comprising a second contact surface; and a conductive filler disposed on at least one contact surface from among the first contact surface and the second contact surface to increase a contact area of the at least one contact surface.

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

A printed structure includes a destination substrate comprising two or more contact pads disposed on or in a surface of the destination substrate, a component disposed on the surface, and two or more electrically conductive connection posts. Each of the connection posts extends from a common side of the component. Each of the connection posts is in electrical and physical contact with one of the contact pads. The component is tilted with respect to the surface of the destination substrate. Each of the connection posts has a flat distal surface.

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).