A semiconductor structure includes providing a substrate including a first surface and a second surface opposite to the first surface. The first surface is a functional surface. The method also includes forming a plastic seal layer on the first surface of the substrate, and performing a thinning-down process on the second surface of the substrate after forming the plastic seal layer. The plastic seal layer provides support for the substrate during the thinning-down process, and thus warping or cracking of the plastic seal layer 240 may be avoided. In addition, the plastic seal layer can also be used as a material for packaging the substrate. Therefore, after the thinning-down process, the plastic seal layer does not need to be removed. As such, the fabrication process is simplified, and the production cost is reduced.

A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.

An electronic component includes a substrate having a first main surface on one side and a second main surface on the other side, a chip having a first chip main surface on one side and a second chip main surface on the other side, and a plurality of electrodes formed on the first chip main surface and/or the second chip main surface, the chip being arranged on the first main surface of the substrate, a sealing insulation layer that seals the chip on the first main surface of the substrate such that the second main surface of the substrate is exposed, the sealing insulation layer having a sealing main surface that opposes the first main surface of the substrate, and a plurality of external terminals formed to penetrate through the sealing insulation layer so as to be exposed from the sealing main surface of the sealing insulation layer, the external terminals being respectively electrically connected to the plurality of electrodes of the chip.

Embodiments of packaged semiconductor devices and methods of making thereof are provided herein, which include a semiconductor die having a plurality of pads on an active side; a dummy die having a plurality of openings that extend from a first major surface to a second major surface opposite the first major surface, wherein the plurality of openings are aligned with the plurality of pads; and a silicone-based glue attaching the dummy die to the active side of the semiconductor die, wherein a plurality of bondable surfaces of the semiconductor die are exposed through the plurality of openings of the dummy die.

A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.

A semiconductor device includes an electronic circuit, an interconnection contact such as a solder ball, and a plate configured to concentrate magnetic flux to a predetermined area. The plate is electrically conductive, and it is electrically connected to the electronic circuit.

Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.

Embodiments of packaged semiconductor devices and methods of making thereof are provided herein, which include a semiconductor die having a plurality of pads on an active side; a dummy die having a plurality of openings that extend from a first major surface to a second major surface opposite the first major surface, wherein the plurality of openings are aligned with the plurality of pads; and a silicone-based glue attaching the dummy die to the active side of the semiconductor die, wherein a plurality of bondable surfaces of the semiconductor die are exposed through the plurality of openings of the dummy die.

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Wafers include multiple bulk redistribution layers. A contact pad is formed on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.