Methods for die attachment of multichip and single components including flip chips may involve printing a sintering paste on a substrate or on the back side of a die. Printing may involve stencil printing, screen printing, or a dispensing process. Paste may be printed on the back side of an entire wafer prior to dicing, or on the back side of an individual die. Sintering films may also be fabricated and transferred to a wafer, die or substrate. A post-sintering step may increase throughput.

The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

An electronic device according to a present disclosure includes a semiconductor substrate, a chip, and a connection part. The chip has a different thermal expansion rate from that of the semiconductor substrate. The connection part includes a porous metal layer for connecting connection pads that are arranged on opposing principle surfaces of the semiconductor substrate and the chip.

Electronic assemblies may be fabricated with interconnects of different types present in multiple locations and comprising fused copper nanoparticles. Each interconnect or a portion thereof comprises a bulk copper matrix formed from fusion of copper nanoparticles or a reaction product formed from copper nanoparticles. The interconnects may comprise a copper-based wire bonding assembly, a copper-based flip chip connection, a copper-based hermetic seal assembly, a copper-based connector between an IC substrate and a package substrate, a copper-based component interconnect, a copper-based interconnect comprising via copper for establishing electrical communication between opposite faces of a package substrate, a copper-based interconnect defining a heat channel formed from via copper, and any combination thereof.

An electroplating method that is a conventional method has had a problem that it is difficult to manufacture fine pillars without being affected by an undercut. Furthermore, an electroless plating method has had a problem that it is difficult to manufacture pillars having the same shape without any void. The inventors have performed intensive investigations to solve the above problems and, as a result, have found that fine conductive pillars with a high aspect ratio can be readily manufactured on a substrate having an electrode section in such a manner that after a conductive paste containing metal micro-particles is applied in a reduced pressure state, the conductive paste is exposed to standard pressure. The present invention has a particular effect on the manufacture of a metal pillar that is a terminal for flip-chip mounting.

An electroplating method that is a conventional method has had a problem that it is difficult to manufacture fine pillars without being affected by an undercut. Furthermore, an electroless plating method has had a problem that it is difficult to manufacture pillars having the same shape without any void. The inventors have performed intensive investigations to solve the above problems and, as a result, have found that fine conductive pillars with a high aspect ratio can be readily manufactured on a substrate having an electrode section in such a manner that after a conductive paste containing metal micro-particles is applied in a reduced pressure state, the conductive paste is exposed to standard pressure. The present invention has a particular effect on the manufacture of a metal pillar that is a terminal for flip-chip mounting.

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.

A microelectronic device has bump bond structures on input/output (I/O) pads. The bump bond structures include copper-containing pillars, a barrier layer including cobalt and zinc on the copper-containing pillars, and tin-containing solder on the barrier layer. The barrier layer includes 0.1 weight percent to 50 weight percent cobalt and an amount of zinc equivalent to a layer of pure zinc 0.05 microns to 0.5 microns thick. A lead frame has a copper-containing member with a similar barrier layer in an area for a solder joint. Methods of forming the microelectronic device are disclosed.