Patent classifications
H01L2224/11602
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.
Joint structure for metal pillars
A female structure embedding a first metal pillar and a male structure embedding a second metal pillar. The female structure and the male structure can be locked in with each other, the embedded first metal pillar electrically coupled to the second metal pillar through a metal block. The metal block is electrically coupled to a bottom surface of the first metal pillar, and the metal block wraps peripheral surface of a top end of the second metal pillar. A first embodiment shows the metal block is formed by electroless deposition after matching the female structure to the male structure. A second embodiment shows the metal block is a solder joint.
Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.
ENABLING MICRO-BUMP ARCHITECTURES WITHOUT THE USE OF SACRIFICIAL PADS FOR PROBING A WAFER
Methods for enabling micro-bump architectures without the use of sacrificial pads for probing a wafer are described. A method includes forming: (1) a first bump in accordance with a specified first diameter, and (2) a first set of bumps in accordance with a specified second diameter, smaller than the specified first diameter. The first bump is used for probing a portion of the wafer associated with the first set of bumps. Both the first bump and the first set of bumps are then removed. The method includes forming: (1) a second set of bumps, in place of the first bump, where each of the second set of bumps is formed in accordance with the specified second diameter, and (2) a third set of bumps, in place of the first set of bumps, where each of the third set of bumps is formed in accordance with the specified second diameter.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.
Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.
SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME
A semiconductor package and a method for making the same are provided. The method includes: providing a package substrate having a first surface and a second surface opposite to the first surface; mounting a plurality of conductive blocks onto the first surface of the package substrate; forming at least one conductive bump on each of the conductive blocks; forming a first encapsulant on the first surface of the package substrate to encapsulate the conductive blocks and the conductive bump on each of the conductive blocks; and grinding the first encapsulant to remove an upper portion of the first encapsulant and an upper portion of the conductive bump on each of the conductive blocks, such that an exposed surface of the conductive bump on each of the conductive blocks is at a same height relative to the first surface of the package substrate.
Semiconductor structure with oval shaped conductor
A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.