An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material.

A lamination structure including a substrate, a first metal pattern layer, a molding layer and a second metal pattern layer. The first metal pattern layer is formed on the substrate. At least a part of the molding layer and the first metal pattern layer are located on a layer. The second metal pattern layer is formed on the first metal pattern layer and has an opening pattern exposing the molding layer. The second metal pattern layer has a top part and a bottom part that are opposite to each other. The top part and the bottom part each have a rounded corner on an edge adjacent to the opening pattern.