Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate, a conductive through electrode, an insulating film, a bump and a connection layer, wherein the connection layer comprises a patternable material with conductive particles. The conductive through electrode penetrates through the semiconductor substrate. The patternable material comprises photosensitive material. The photosensitive material is a photoresist or polyimide. The conductive particles comprise copper (Cu), nickel (Ni), gold (Au), or silver (Ag). The connection layer is formed by spin coating, CVD (chemical vapor deposition) process or PVD (physical vapor deposition) process. The insulating film surrounds the conductive through electrode and electrically isolates the conductive through electrode from the is substrate. The bump is disposed over the conductive through electrode. The connection layer is disposed over the bump.

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

A semiconductor device including a substrate including a first conductive pad on a first surface thereof, at least one first bump structure on the first conductive pad, the first bump structure including a first connecting member and a first delamination prevention layer, the first delamination prevention layer on the first connecting member and having a greater hardness than the first connecting member, and a first encapsulant above the first surface of the substrate and surrounding the first bump structure may be provided.

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

The present disclosure provides a semiconductor structure including a substrate; a redistribution layer (RDL) disposed over the substrate, and including a dielectric layer over the substrate, a conductive plug extending within the dielectric layer, and a bonding pad adjacent to the conductive plug and surrounded by the dielectric layer; and a conductive bump disposed over the conductive plug, wherein the bonding pad is at least partially in contact with the conductive plug and the conductive bump. Further, a method of manufacturing the semiconductor structure is also provided.

A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti). The UBM stack eliminates the need for magnetic materials such as nickel (Ni) in the stack, making the stack suitable for cryogenic applications.

Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.

Disclosed are techniques for selectively boosting conductive pillar bumps. In an aspect, an apparatus includes a plurality of metal pads, a first set of boosting pads attached to a first set of the plurality of metal pads, a first set of conductive pillar bumps attached to the first set of boosting pads, a second set of conductive pillar bumps attached to a second set of the plurality of metal pads, wherein heights of the first set of conductive pillar bumps are shorter than heights of the second set of conductive pillar bumps, and wherein heights of the first set of boosting pads plus the heights of the first set of conductive pillar bumps are within a tolerance threshold of the heights of the second set of conductive pillar bumps, and solder attached to the first set of conductive pillar bumps and the second set of conductive pillar bumps.