In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess.

In an embodiment a method includes providing a semiconductor chip having a plurality of contact pins, at least one positioning pin and an underside, wherein the contact pins and the positioning pin protrude from the underside, respectively, wherein the contact pins are configured for making electrical contact with the semiconductor chip, wherein the positioning pin narrows in a direction away from the underside, and wherein the positioning pin protrudes further from the underside than the contact pins, providing a connection carrier having a plurality of contact recesses, at least one positioning recess and an upper side, wherein each contact recess is at least partially filled with a solder material, heating the solder material in the contact recesses to a joining temperature at which the solder material at least partially melts and placing the semiconductor chip on the connection carrier, wherein each contact pin is inserted into a contact recess and the positioning pin is inserted into the positioning recess.

A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.

A bonded body includes: a first base body including a first wiring, a first electrode made of an electroplating film and including a first surface having a first region covering a periphery of an end portion of the first wiring and a second region covering the end portion of the first wiring, and a first passivation layer made of an insulating material and covering a periphery of the first electrode; a second base body including a second electrode; and solder disposed between the first region of the first electrode and the second electrode.

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

An electronic device includes a substrate, a semiconductor die, and a molded package structure that encloses a portion of the semiconductor die and extends to a portion of the substrate. A sensor surface extends along a side of the semiconductor die, and conductive terminals extend outward from the side and have ends soldered to conductive features of the substrate. The side of the semiconductor die is spaced apart from the substrate and the conductive terminals forming a cage structure that laterally surrounds the sensor surface. The molded package structure has a cavity that extends between the sensor surface and the substrate, and the cavity extends in an interior of a cage structure formed by the conductive terminals.

No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

A three-dimensional fan-out memory package structure and a packaging method are disclosed. The package structure includes a three-dimensional fan-out memory package unit, which includes: a memory chip stack having at least two memory chips laminated in a stepped configuration, each memory chip is provided with a bonding pad; first metal connection pillars formed on the bonding pads; second metal connection pillars; a first encapsulating layer; a first rewiring layer formed on a back side of the memory chip stack; a second rewiring layer formed over a front side of the memory chip stack; and metal bumps. The package structure further includes: at least one peripheral circuit chip electrically connected with the first rewiring layer; and a second encapsulating layer, which encapsulates the peripheral circuit chip. The package structure allows for high-density and high-integration of line width/line spacing. The process time can be shortened, and the efficiency is high.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first electronic component, a second electronic component, a bonding wire, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The first electronic component is disposed on the upper surface of the substrate. The bonding wire electrically connects the first electronic component and the substrate and extends within the substrate. The second electronic component is disposed on the upper surface of the substrate. The second electronic component has an active surface facing the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant extends within the substrate and encapsulates the bonding wire.