Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.

A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.

A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stacking structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface; and a conductive connecting layer comprising a first conducting part, comprising a first outer boundary, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conducting part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conducting part.

A sintered body of silver fine particles for a bonding member to bond components of a semiconductor device, wherein an activation energy for creep of the sintered body of the silver fine particles is from 0.4 to 0.75 times that of an activation energy for a lattice diffusion of bulk silver.

Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

Apparatuses, systems, and methods associated with spacer elements for maintaining a distance between a substrate and component during reflow are disclosed herein. In embodiments, a substrate assembly may include a substrate and a component. The component may be coupled to the substrate via a solder joint, wherein the solder joint may include a spacer element and solder, the spacer element to maintain a distance between the substrate and the component. Other embodiments may be described and/or claimed.

An electronic device and associated methods are disclosed. In one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. In selected examples, a layer including tin is used in conjunction with other interface layers. In selected examples, a layer including tin is used in all vertical connections.

A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section view, and a distance from the first position to the first out contour is greater than that from the second position to the first outer contour.

A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.