A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

An electronic device includes a die, a packages structure, and a multilevel redistribution structure having a first via, a first level, a second via, a second level, and passivation material. The first level has a conductive antenna, the first via extends between the conductive antenna and a conductive terminal of the die, and the passivation material extends between the first and second levels. The second via extends through the passivation material between the first and second levels. The second level has a conductive reflector.

A semiconductor package includes a redistribution substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip mounted on the first surface of the redistribution substrate, an under bump interconnection layer on the second surface of the redistribution substrate, an electronic device mounted on the under bump interconnection layer, and a solder bump disposed on the under bump interconnection layer and horizontally spaced apart from the electronic device. The under bump interconnection layer includes conductive patterns respectively connected to the electronic device and the solder bump, and a passivation layer covering the conductive patterns. The passivation layer includes a plurality of trenches disposed between the electronic device and the solder bump.

Provided is a semiconductor light emitting device including a semiconductor structure including a first semiconductor layer, a light emitting layer, and a second semiconductor layer, a side extension structure disposed adjacent to a sidewall of the semiconductor structure, a first electrode having a first portion extending through the second semiconductor layer and the light emitting layer and electrically connected to the first semiconductor layer, and a second portion extending on an upper surface of the side extension structure in a horizontal direction, and a second electrode having a first portion electrically connected to the second semiconductor layer and a second portion extending on the upper surface of the side extension structure in the horizontal direction.

A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

An electronic device includes a via-array substrate, an outer layer, and an alignment substrate. The via-array substrate has a plurality of first vias. The outer layer has a plurality of second vias and is disposed on a side of the via-array substrate. The first vias are greater in distribution density or quantity than the second vias. A part of the first vias is electrically connected to the second vias, and another part of the first vias is electrically floating. The alignment substrate includes a core layer disposed on the outer layer, a plurality of conductive traces, a plurality of interconnecting pads, and a plurality of alignment mark pads. The conductive traces are disposed in the core layer. The interconnecting pads and the alignment mark pads are disposed on a surface of the core layer located away from the outer layer. A part of the conductive traces electrically connects a part of the interconnecting pads and a part of the first vias. A pattern of each of the alignment mark pads is different from a pattern of each of the interconnecting pads.

A method includes forming a reconstructed wafer, which includes placing a plurality of device dies over a carrier, encapsulating the plurality of device dies in an encapsulant, and forming a redistribution structure over the plurality of device dies and the encapsulant. The redistribution structure includes a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes performing a trimming process on the reconstructed wafer. The trimming process forms a round edge for the reconstructed wafer. A sawing process is performed on the reconstructed wafer, so that the reconstructed wafer includes straight edges.

A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. An opening is formed within metallization layers over the semiconductor substrate and the semiconductor substrate, and an encapsulant is placed to fill the opening. Once the encapsulant is placed, the semiconductor substrate is singulated to separate the devices. By recessing the material of the metallization layers and forming the opening, delamination damage may be reduced or eliminated.