A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.

A power overlay (POL) module includes a semiconductor device having a body, including a first side and an opposing second side. A first contact pad defined on the semiconductor device first side and a dielectric layer, having a first side and an opposing second side defining a set of first apertures therethrough, is disposed facing the semiconductor device first side. The POL module, includes a metal interconnect layer, having a first side and an opposing second side, the metal interconnect layer second side is disposed on the dielectric layer first side) and extends through the set of first apertures to define a set of vias electrically coupled to the first contact pad. An enclosure defining an interior portion is coupled to the metal interconnect layer first side, and a phase change material (PCM) is disposed in the enclosure interior portion.