This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

A semiconductor package includes a redistribution substrate including a first redistribution layer, a first molding member on the redistribution substrate, a second redistribution layer on an upper surface of the first molding member and having a redistribution pad, an electrical connection pad on an upper surface of a second molding member and electrically connected to the second redistribution layer, and a passivation layer on the second molding member and having an opening exposing at least a portion of the electrical connection pad. The electrical connection pad includes a conductor layer, including a first metal, and a contact layer on the conductor layer and including a second metal. The redistribution pad includes a third metal, different from the first metal and the second metal. The portion of the electrical connection pad, exposed by the opening, has a width greater than a width of the redistribution pad.

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

An imaging device to which a simple mounting method can be applied is configured. The imaging device is provided with an imaging element, a wiring substrate, and a sealing portion. The imaging element is provided with an image pickup chip over which an light transmitting portion transmitting incident light is arranged and which generates an image signal on the basis of the incident light that has passed through the light transmitting portion, and a pad which is arranged on a bottom surface of the image pickup chip different from a surface on which the light transmitting portion is arranged, which the pad transmitting the generated image signal. The wiring substrate has wiring connected to the pad and extending to a region outside the imaging element, and has the imaging element arranged on a surface thereof. The sealing portion is arranged adjacent to a side surface which is a surface adjacent to the bottom surface of the imaging element, and seals the imaging element.

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.