Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL is electrically coupled to the second surface of the first die by solder interconnects, and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by non-solder interconnects.

A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

An electronic device including a connection element is provided. The connection element includes a first insulation layer and a second insulation layer. The first insulation layer has a first opening. A sidewall of the first insulation layer at the first opening has roughness different from roughness of a top surface of the first insulation layer. The second insulation layer is disposed on the first insulation layer, and the second insulation layer has a second opening. The sidewall of the first insulation layer at the first opening is exposed by the second opening. A method of fabricating an electronic device is also provided.

An electronic device including a connection element is provided. The connection element includes a first metal layer, a first insulation layer, and a second insulation layer. The first insulation layer is disposed on the first metal layer and has a first hole and a second hole. The second insulation layer is disposed on the first insulation layer. The first hole exposes a portion of the first metal layer, and the second insulation layer extends into the second hole. A method of fabricating an electronic device is also provided.

A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.

This disclosure provides an LED chip packaging module includes: a re-distribution layer RDL, where a plurality of first pads are disposed on a lower surface of the RDL; a micro light emitting diode micro LED chip disposed on an upper surface of the RDL, where an electrode of the micro LED chip faces the upper surface of the RDL and is connected to the RDL; and a micro integrated circuit micro IC disposed on the upper surface of the RDL, where an electrode of the micro IC faces the upper surface of the RDL and is connected to the RDL. The first pad is electrically connected to the micro IC by using the RDL. The micro IC is electrically connected to the micro LED chip by using the RDL. The first pad is configured to receive an external drive signal.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.