A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die.

A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.

A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.

A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.