In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.

A laser device comprises a carrier, an optoelectronic component provided on the carrier, said component being designed to emit laser radiation, and an optical element designed to form the laser radiation emitted by the optoelectronic component, wherein: the optical element has a first layer that is at least partially transparent to the laser radiation, with a first refractive index, and a second layer that is at least partially transparent to the laser radiation, with a second refractive index; the first layer being applied to the optoelectronic component and having a surface with an imprinted structure; and the second layer is applied to the first layer, on the surface (24) having the imprinted structure.

A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.

The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.

In an embodiment, a semiconductor module includes a low side switch and a high side switch. The low side switch and the high side switch are arranged laterally adjacent one another and coupled in series between a ground package pad and a voltage input (VIN) package pad of the semiconductor module and form a half bridge configuration having an output node. The semiconductor module further includes a first capacitor pad coupled to ground potential and a second capacitor pad coupled to a VIN potential. The first capacitor pad is arranged vertically above the low side switch and the second capacitor pad is arranged vertically above the high side switch.

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.

An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.