A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

A display device may include a light emitting element including a first end having a first surface, and a second end having a second surface parallel to the first surface, an organic pattern that overlaps the light emitting element and exposes the first and second surfaces, a first electrode disposed on a substrate and electrically contacting the first end, and a second electrode disposed on the substrate and spaced apart from the first electrode, and electrically contacting the second end. A surface area of the first surface may be less than that of the second surface. A top surface of the organic pattern may be a curved surface.

A display device may include a conductive pattern disposed on a substrate. A passivation layer may be disposed on the conductive pattern. A first shielding electrode and a second shielding electrode that may be disposed on the passivation layer may be spaced apart from each other. A first electrode may be disposed on the first shielding electrode. A second electrode may be disposed on the second shielding electrode. A light emitting element may be electrically connected between the first electrode and the second electrode. A first distance between the first shielding electrode and the second shielding electrode may be less than a second distance between the first electrode and the second electrode.

An electronic package is provided and includes an electronic element connected to a plurality of inductor circuits embedded in an insulator of a package substrate by fan-out conductive copper pillars, and at least one shielding layer non-electrically connected to the inductor circuits, where the shielding layer includes a plurality of line segments not connected to each other, such that the shielding layer shields the inductor circuits, thereby achieving the electrical requirements of high-current products while improving the inductance value and quality factor.

A display device includes: a power source line; a plurality of gate lines each extending in a first direction and arranged along a second direction in a plan view; a plurality of pixels connected to the power source line and the gate lines; and a plurality of vertical lines each extending in the second direction and arranged along the first direction in the plan view, wherein the vertical lines include a plurality of gate connection lines and a plurality of dummy lines between the gate connection lines, wherein the gate connection lines connect the gate lines to a gate driver, wherein the dummy lines are connected to the power source line, and wherein a distance between the dummy lines spaced apart from each other with at least one of the gate connection lines interposed therebetween is constant throughout.

The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 μm. Corresponding methods of producing multi-chip assemblies are also described.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.