Patent classifications
H01L2224/4321
GOLD-COATED SILVER BONDING WIRE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A gold-coated silver bonding wire includes: a core material containing silver as a main component; and a coating layer provided on a surface of the core material and containing gold as a main component. The gold-coated silver bonding wire contains gold in a range of not less than 2 mass % nor more than 7 mass %, and at least one sulfur group element selected from the group consisting of sulfur, selenium, and tellurium in a range of not less than 1 mass ppm nor more than 80 mass ppm, with respect to a total content of the bonding wire.
Cu alloy bonding wire for semiconductor device
The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.
Bonding wire for semiconductor device
A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:
Strength ratio=ultimate strength/0.2% offset yield strength.(1)
Cu ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE
The present invention provides a Cu alloy bonding wire for a semiconductor device, where the bonding wire can satisfy requirements of high-density LSI applications. In the Cu alloy bonding wire for a semiconductor device, the abundance ratio of a crystal orientation <110> having an angular difference of 15 degrees or less from a direction perpendicular to one plane including a wire center axis to crystal orientations on a wire surface is 25% or more and 70% or less in average area percentage.
Connection pads for low cross-talk vertical wirebonds
Wirebond bondpads on semiconductor packages that result in reduced cross-talk and/or interference between vertical wires are disclosed. The vertical wirebonds may be disposed in the semiconductor package with stacked dies, where the wires are substantially normal to the bondpads to which the vertical wirebonds are attached on the dies. The wirebond bondpads may include signal pads that carry input/output (I/O) to/from the die package, as well as ground bondpads. The bondpads may have widths that are greater than the space between adjacent bondpads. Bondpads may be fabricated to be larger than the size requirements for reliable wirebond formation on the bondpads. For a fixed pitch bondpad configuration, the size of the signal bondpads adjacent to the ground bondpads may be greater than half of the pitch. By increasing the size of the signal bondpads adjacent to a ground line relative to the space therebetween, improved cross-talk performance may be achieved.
BONDING WIRE FOR SEMICONDUCTOR DEVICE
There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.
COATED WIRE
A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself is a silver-based wire core, wherein the coating layer is a double-layer comprised of a 1 to 100 nm thick inner layer of nickel or palladium and an adjacent 1 to 250 nm thick outer layer of gold, characterized in that the wire exhibits a total carbon content of 40 wt.-ppm.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
A semiconductor package includes a redistribution wiring layer having redistribution wirings stacked in at least two levels; a first semiconductor chip arranged on the redistribution wiring layer; a plurality of second semiconductor chips arranged on the first semiconductor chip; first conductive wires electrically connecting first chip pads of the first semiconductor chip and the redistribution wirings of the redistribution wiring layer; second conductive wires electrically connecting second chip pads of the plurality of second semiconductor chips and the redistribution wirings of the redistribution wiring layer; and a sealing unit disposed on the redistribution wiring layer.
Semiconductor device and method of manufacturing the same
A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.
Bonding wire for semiconductor device
There is provided a bonding wire for a semiconductor device including a coating layer having Pd as a main component on a surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on a surface of the coating layer, the bonding wire further improving 2nd bondability on a Pd-plated lead frame and achieving excellent ball bondability even in a high-humidity heating condition. The bonding wire for a semiconductor device including the coating layer having Pd as a main component on the surface of the Cu alloy core material and the skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing either or both of Pd and Pt in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in the 2nd bondability and excellent ball bondability in the high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.