In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal moulded body 2 as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer 3a with regions of varying thickness. The metal moulded body 2 takes the form here of a flexible contacting film 5 of such a thickness that this contacting film is sintered with its side 4 facing the sintering layer 3a onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal moulded body. The forming of the power semiconductor contact structure is performed firstly by applying a layer of sintering material of locally varying thickness to either the metal moulded body 2 or the substrate, followed by sintering together the contacting film 5 with the substrate 1 by using the properties of the layer of sintering material that are conducive to connection, the contacting film 5 being made to develop its distinct form to correspond to the varying thickness of the layer of sintering material 3a.

A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal moulded body 2 as an electrode, which are sintered one on top of the other by means of a substantially uninterrupted sintering layer 3a with regions of varying thickness. The metal moulded body 2 takes the form here of a flexible contacting film 5 of such a thickness that this contacting film is sintered with its side 4 facing the sintering layer 3a onto the regions of varying thickness of the sintering layer substantially over the full surface area. A description is also given of a method for forming a power semiconductor contact structure in a power semiconductor module that has a substrate and a metal moulded body. The forming of the power semiconductor contact structure is performed firstly by applying a layer of sintering material of locally varying thickness to either the metal moulded body 2 or the substrate, followed by sintering together the contacting film 5 with the substrate 1 by using the properties of the layer of sintering material that are conducive to connection, the contacting film 5 being made to develop its distinct form to correspond to the varying thickness of the layer of sintering material 3a.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.