A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.