H01L2224/484

Package substrate comprising side pads on edge, chip stack, semiconductor package, and memory module comprising same

The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.

DOCUMENT STRUCTURE FORMATION
20240105669 · 2024-03-28 ·

A chip assembly having a carrier having a cavity and at least one carrier contact, a chip arranged in the cavity and having at least one chip contact, and a wirebond wire, which electrically conductively connects the at least one chip contact to the at least one carrier contact, wherein the wirebond wire is flat-pressed in at least one subregion.

Oscillator

An oscillator includes a first resonator element, a first package that accommodates the first resonator element, a relay substrate on which the first package is mounted, a heater element that is attached to the first package or the relay substrate, a second package that accommodates the first package, and a heat insulating member that is provided at least between the second package and the relay substrate or between the relay substrate and the first package.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

SYSTEMS AND METHODS FOR OPTIMIZING LOOPING PARAMETERS AND LOOPING TRAJECTORIES IN THE FORMATION OF WIRE LOOPS

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

SYSTEMS AND METHODS FOR OPTIMIZING LOOPING PARAMETERS AND LOOPING TRAJECTORIES IN THE FORMATION OF WIRE LOOPS

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

Semiconductor device and manufacturing method

A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.

LIGHT-EMITTING ARRANGEMENT AND LIGHT-EMITTING SYSTEM
20190242556 · 2019-08-08 · ·

Described is an arrangement and system for precise angular and directional positioning of light-emitting diodes (LED). An LED component includes a base body with a light-emitting region, a first connector, and a second connector, where the connectors are electrically conductively connected to the light-emitting region. The base body includes at least two fixing regions and the connectors each include a bending portion and a contact area for surface mounting. Each of the bending portions is arranged between the base body and the contact area. A supporting frame includes a plinth region to align the supporting frame on a surface and includes an outwardly open recess, a support region to receive a component in the supporting frame and at least two fixing elements to fix the component above the support region. A base area of the plinth region and a base area of the support region enclose an acute angle.

LIGHT-EMITTING ARRANGEMENT AND LIGHT-EMITTING SYSTEM
20190242557 · 2019-08-08 · ·

Described is an arrangement and system for precise angular and directional positioning of light-emitting diodes (LED). An LED component includes a base body with a light-emitting region, a first connector, and a second connector, where the connectors are electrically conductively connected to the light-emitting region. The base body includes at least two fixing regions and the connectors each include a bending portion and a contact area for surface mounting. Each of the bending portions is arranged between the base body and the contact area. A supporting frame includes a plinth region to align the supporting frame on a surface and includes an outwardly open recess, a support region to receive a component in the supporting frame and at least two fixing elements to fix the component above the support region. A base area of the plinth region and a base area of the support region enclose an acute angle.