A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

The present disclosure A heat dissipation substrate includes: a metal-ceramic composite board, where the metal-ceramic composite board is a metal layer wrapping a ceramic body; a metal oxide layer integrated with the metal layer and formed on an outer surface of the metal layer; and a conductive layer formed on at least a part of an outer surface of the metal oxide layer, where a conductive trace is formed on the conductive layer, and is used to connect with and bear a chip.

The present disclosure A heat dissipation substrate includes: a metal-ceramic composite board, where the metal-ceramic composite board is a metal layer wrapping a ceramic body; a metal oxide layer integrated with the metal layer and formed on an outer surface of the metal layer; and a conductive layer formed on at least a part of an outer surface of the metal oxide layer, where a conductive trace is formed on the conductive layer, and is used to connect with and bear a chip.

A semiconductor apparatus is provided, including: a housing; a heat-dissipation substrate; a first semiconductor chip provided on the heat-dissipation substrate; a temperature detecting unit provided on the housing; a first thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit; and a second thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit, the second thermoelectric member being made of a different material than the first thermoelectric member. The thermal conductivity of the heat-dissipation substrate is higher than the thermal conductivity of the housing.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.