H01L2224/76155

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP
20180026023 · 2018-01-25 · ·

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

BARE DIE INTEGRATION WITH PRINTED COMPONENTS ON FLEXIBLE SUBSTRATE WITHOUT LASER CUT

Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.

BARE DIE INTEGRATION WITH PRINTED COMPONENTS ON FLEXIBLE SUBSTRATE

Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among others, where the surface of the electronic circuit component is at the same level as the associated substrate, the surface of the electronic circuit component holding connection pads. A gap exists between the electronic circuit component, and the end of an opening within the substrate. This gap is filled with a filler material, such as a bonding material. The bonding material also used to encapsulate or bond together the back side of the substrate and electronic circuit component. During the manufacturing process, the front surface of the electronic circuit component (which includes the contact pads) and the front surface of the substrate which includes electronic circuitry are held in an adhesive relationship by a flat material having an upper surface which includes adhesive or sticky material (such as PDMS). Once the flat material is removed the planar flat or level upper surface can readily accept the formation of conductive traces by the use of inkjet printing or other technologies.

Semiconductor Device and Method of Stacking and Interconnecting Semiconductor Assemblies Using Conductive Layer with Graphene Core Shells

A semiconductor device has a plurality of stacked semiconductor assemblies. Each semiconductor assembly has a first electrical component, and an electrical connector disposed adjacent to the first electrical component. A conductive layer with a graphene core shell is formed between the first electrical component and electrical connector. The graphene core shell has a copper core or silver core. The conductive layer has a plurality of cores covered by graphene and the graphene is interconnected within the conductive layer to form an electrical path. The conductive layer has a thermoset material or polymer or composite epoxy type matrix. A second electrical component is disposed adjacent to a side of the electrical connector opposite the first electrical component. An encapsulant is deposited around the first electrical component, second electrical component, and electrical connector. The conductive layer is formed between the second electrical component and electrical connector over the encapsulant.