A method for bonding with precision alignment. A first bonding surface is bonded with a second bonding surface, where features on the first and second bonding surfaces are precisely overlaid during the bonding. An etch is then performed on the first and/or second bonding surfaces to create recesses in the first and/or second bonding surfaces. Precision alignment of the first and second bonding surfaces is then enabled by a volatile fluid deployed between the first and second bonding surfaces, where the recesses enable removal of the volatile fluid from a bonding interface during and after the bonding.

An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises lower and upper structures. The lower structure includes a first semiconductor substrate, a first pad, and a first dielectric layer. The upper structure includes a second semiconductor substrate, a second pad, and a second dielectric layer. The upper and lower structures are bonded to each other to allow the first and second pads to come into contact each other and to allow the first and second dielectric layers to come into contact each other. A first interface between the first and second pads is at a level different from that of a second interface between the first and second dielectric layers. A first area of the first pad is greater than a second area of the second pad. A second thickness of the second pad is different from a first thickness of the first pad.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes providing a first element having a first bonding surface, providing a second element having a second bonding surface, slightly etching the first bonding surface, treating the first bonding surface with a terminating liquid treatment to terminate the first bonding surface with a terminating species, and directly bonding the first bonding surface to the second bonding surface without the use of an intervening adhesive and without exposing the first bonding surface to plasma.

A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

Electrical connection between electrodes provided respectively at facing positions in joint surfaces of substrates to be joined by chip lamination technology is conducted more securely. A method of manufacturing a semiconductor device includes: a first step of embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate; a second step of subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layers; a third step of laminating insulating films of a uniform thickness over the entire joint surfaces; a fourth step of forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate; a fifth step of causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other; and a sixth step of heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.