Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact or the second bonding contact is made of an indiffusible conductive material.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact or the second bonding contact is made of an indiffusible conductive material.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or dishing of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a first memory deck above the substrate, a first channel structure, a first inter-deck plug above and in contact with the first channel structure, a second memory deck above the first inter-deck plug, and a second channel structure above and in contact with the first inter-deck plug. The first memory deck includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure extends vertically through the first memory deck. The first inter-deck plug includes single-crystal silicon. The second memory deck includes a second plurality of interleaved conductor layers and dielectric layers. The second channel structure extends vertically through the second memory deck.

Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or dishing of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.

Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.