H01L2224/80065

Microstructure modulation for 3D bonded semiconductor structure with an embedded capacitor

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic capacitor plate structure embedded therein, wherein each metallic capacitor plate structure has a columnar grain microstructure. A high-k dielectric material is present between the first and second metallic capacitor plate structures. The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q.

Hybrid bonding systems and methods for semiconductor wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR CONTAINING AN EMBEDDED RESISTOR STRUCTURE
20180240859 · 2018-08-23 ·

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic pad structure embedded therein, wherein each metallic pad structure has a columnar grain microstructure. A metal resistor structure is embedded in one of the first bonding oxide layer or the second bonding oxide and is present between the first and second metallic pad structures.

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR
20180240860 · 2018-08-23 ·

A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic capacitor plate structure embedded therein, wherein each metallic capacitor plate structure has a columnar grain microstructure. A high-k dielectric material is present between the first and second metallic capacitor plate structures. The presence of the columnar grain microstructure in the metallic capacitor plate structures can provide an embedded capacitor that has an improved quality factor, Q.

Gas-controlled bonding platform for edge defect reduction during wafer bonding

A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

IMAGING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC DEVICE
20180166490 · 2018-06-14 ·

There is provided an imaging device including: a first semiconductor substrate (21) having a first region (22, R11) that includes a photoelectric conversion section (67) and a via portion (51), a second region (R12) adjacent to the first region, a connection portion (53, 84, 85) disposed at the second region, and a second semiconductor substrate (81), wherein the connection portion electrically couples the first semiconductor substrate to the second semiconductor substrate in a stacked configuration, and wherein a width of the connection portion is greater than a width of the via portion.

3D bonded semiconductor structure with an embedded capacitor

A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed.

GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING
20180082863 · 2018-03-22 ·

A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING
20180082864 · 2018-03-22 ·

A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

Gas-controlled bonding platform for edge defect reduction during wafer bonding

A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.