An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

A method for bonding a first substrate to a second substrate on mutually facing contact surfaces of the substrates, wherein the first substrate is mounted on a first chuck and the second substrate is mounted on a second chuck, and wherein a plate is arranged between the second substrate and the second chuck, wherein the second substrate with the plate is deformed with respect to the second chuck before and/or during the bonding. Furthermore, the present invention relates to a corresponding device and a corresponding plate.

An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

A method for low temperature bonding of substrates involves the following steps: A first substrate and a second substrate are provided; the first substrate and the second substrate are aligned; the first substrate and the second substrate are prebonded by a fusion prebonding process; and the first substrate and the second substrate are bonded by applying an electric voltage between the first substrate and the second substrate, wherein said voltage comprises a pulsed or AC component.

A method of manufacturing a semiconductor structure includes the following steps. A die is provided. The die includes an interconnect structure and an active pad electrically connected to the interconnect structure. A dielectric layer is formed over the die, wherein the dielectric layer is a single layer. An active bonding via is formed in the dielectric layer. The active pad has a first surface facing the interconnect structure and a second surface opposite to the first surface, the active bonding via has a third surface facing the interconnect structure and a fourth surface opposite to the third surface, and the second surface of the active pad is disposed between the third surface and the fourth surface of the active bonding via.

The present disclosure relates to a semiconductor packaging alignment apparatus and a method thereof, and the semiconductor packaging alignment apparatus includes a radiation source that radiates radiation to a plurality of semiconductor chips, a radiation sensor that detects the radiation passing through the plurality of semiconductor chips, a head that is coupled with one of the radiation source or the radiation sensor, an alignment part that aligns and bonds the plurality of semiconductor chips based on detection information acquired by the radiation sensor, and a process that controls at least one of the radiation source, the head, the radiation sensor, or the alignment part, or any combination thereof.