A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits includes a first logic circuit and a second logic circuit, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of on-chip RF circuits, and where a portion of interconnections between the first logic circuit and the second logic circuit includes the plurality of on-chip RF circuits.

A semiconductor device according to the present embodiment includes a first chip and a second chip. A first pad is disposed so as to be exposed from a first region on a first surface. A first mark is provided by a first pattern and is disposed so as to be exposed from a second region. The second chip includes a second substrate, a second wire, a second pad, and a second mark. The second wire is disposed on the second substrate. The second pad is disposed so as to be exposed from a third region on a second surface, and is electrically connected to the second wire and the first pad. The second mark is provided by a second pattern corresponding to the first pattern, is disposed so as to be exposed from a fourth region, and has a thinner thickness than the second pad.

A 3D semiconductor device, the device including: a first die including first transistors and a first interconnect; a second die including second transistors and a second interconnect; and a third die including third transistors and a third interconnect, where the first die is overlaid by the second die, where the first die is overlaid by the third die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 20% larger than the second die area, where the second die is pretested, where the second die is bonded to the first die, where the bonded includes metal to metal bonding, where the first die includes at least two first alignment marks positioned close to a first die edge of the first die, and where the third die is bonded to the first die.

A bond head assembly for a bonding machine is provided. The bond head assembly includes a body portion and a bonding tool for bonding a semiconductor element to a substrate. The bonding tool is secured to the body portion. The bond head assembly also includes at least one reflective optical element carried by the bond head assembly. The at least one reflective optical element is configured to be positioned along an optical path of the bonding machine such that a vision system of the bonding machine is configured to view a portion of the semiconductor element while being carried by the bonding tool prior to bonding of the semiconductor element to the substrate.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

A 3D semiconductor device, the device including: a first die comprising first transistors and a first interconnect; and a second die comprising second transistors and a second interconnect, wherein said first die is overlaid by said second die, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is pretested, wherein said second die is bonded to said first die, wherein said bonded comprises metal to metal bonding, wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

A 3D semiconductor device, the device including: a first die comprising first transistors and a first interconnect; and a second die comprising second transistors and a second interconnect, wherein said first die is overlaid by said second die, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is pretested, wherein said second die is bonded to said first die, wherein said bonded comprises metal to metal bonding, wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

A bonding system includes a first holder and a second holder arranged to be spaced apart from each other in a vertical direction; a position adjuster configured to move the first holder and the second holder relatively to perform a position adjustment in a horizontal direction between a first substrate held by the first holder and a second substrate held by the second holder; a pressing unit configured to press the first substrate and the second substrate against each other; a measuring unit configured to measure a position deviation between an alignment mark on the first substrate and an alignment mark on the second substrate, the first substrate and the second substrate being bonded by the pressing unit; and a position adjustment controller configured to control the position adjustment in the horizontal direction in a currently-performed bonding processing based on the position deviation generated in a previously-performed bonding processing.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.

Provided is a bonding method for directly bonding an electrode part of a chip component to a bonding part provided on a substrate that is a bonding target, the method comprising: a step for placing the substrate on a stage inside a liquid vessel; a step for injecting liquid into the liquid vessel; and a step for bonding the electrode part of the chip component to the bonding part (electrode part) of the bonding target by superimposing the chip component held by a bonding head in the liquid stored in the liquid vessel over the bonding target and then applying pressure thereto.