A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.

A manufacturing method for manufacturing a stacked substrate by bonding two substrates includes: acquiring information about crystal structures of a plurality of substrates; and determining a combination of two substrates to be bonded to each other, based on the information about the crystal structures. In the manufacturing method described above, the information about the crystal structures may include at least one of plane orientations of bonding surfaces and crystal orientations in a direction in parallel with the bonding surfaces. In the manufacturing methods described above, the determining may include determining a combination of the two substrates with a misalignment amount after bonding being equal to or smaller than a predetermined threshold.

A substrate processing apparatus includes a chuck configured to attract and hold a substrate; an observer configured to observe multiple positions within a second surface of the substrate attracted to and held by the chuck, the second surface being opposite to a first surface thereof which is in contact with the chuck; and an analyzer configured to analyze observation results of the multiple positions. When a singularity regarding a height from a surface of the chuck attracting and holding the substrate exists on the second surface, the analyzer specifies a position of the singularity on the chuck.

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.