An apparatus for wafer bonding includes a first bearing table configured to hold a first wafer provided with at least one first alignment mark; a second bearing table, opposite to the first bearing table, and configured to hold a second wafer provided with at least one second alignment mark; an alignment component, located on at least a side of the first or second bearing table, and configured to determine first and second position parameters of the first and second alignment marks, respectively, by using an optical beam; a mobile component, connected to the first and second bearing tables, and configured to adjust, according to the first an second position parameters, a relative position between the first and second wafers until a relative position between the first and second alignment marks satisfies a predetermined bonding condition; and a bonding component, connected to the first and second bearing tables, and configured to bond the first wafer to the second wafer.

A method is provided and includes the following steps. A first wafer is coupled to a first support of a bonding tool and a second wafer is coupled to a second support of the bonding tool. The second wafer is bonded to the first wafer with the first wafer coupled to the first support. Whether a bubble is between the bonded first and second wafers in the bonding tool is detected.

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

A wafer-level semiconductor die attachment method includes placing a semiconductor die of a plurality of semiconductor dies at an initial placement position to overlap a sub-mount pad on a sub-mount of a pre-singulated wafer. A die pad of the semiconductor die comes in contact with a solder layer deposited over the sub-mount pad. The semiconductor die and the sub-mount include a plurality of die and sub-mount mating features, respectively. The solder layer is heated locally to temporarily hold the semiconductor die at the initial placement position. The pre-singulated wafer is reflowed, when each semiconductor die is temporarily held at the corresponding initial placement position. During reflow, each semiconductor die slides from the initial placement position and a contact is established between the corresponding plurality of die and sub-mount mating features. Thereby, each semiconductor die is permanently attached to the corresponding sub-mount.

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.

A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact in a state where a temperature difference is generated therebetween, to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate, wherein enlargement of the contact regions starts before positional misalignment between the first substrate and the second substrate exceeds a threshold, and the threshold is set such that positional misalignment after the first substrate and the second substrate are bonded does not exceed a tolerated value.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

A package structure and method for forming the same are provided. The package structure includes a first die, and the first die includes a first magnetic pad formed over a first substrate. The package structure includes a second die, and the second die includes a second magnetic pad formed over a second substrate. The package structure also includes a hybrid bonding structure formed between the first die and the second die of the second wafer. The hybrid bonding structure includes a magnetic bonding structure which is made of the first magnetic pad and the second magnetic layer.

In an embodiment, a device includes: an interconnect structure over a substrate, the interconnect structure including a first metal line and a second metal line, the first metal line longer than the second metal line; a surface dielectric layer over the interconnect structure; a plurality of first vias in the surface dielectric layer; a first bonding pad in the surface dielectric layer, where the first bonding pad is connected to a first end of the first metal line through the first vias; a plurality of second vias in the surface dielectric layer; a second bonding pad in the surface dielectric layer, the second bonding pad and the first bonding pad separate from each other, where the second bonding pad is connected to a second end of the first metal line through the second vias; and a third bonding pad in the surface dielectric layer, where the third bonding pad is connect to the second metal line through a third via.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.