A bonding apparatus includes a first holder configured to hold a first substrate divided into multiple chips with a tape and a ring frame therebetween, the first substrate being attached to the tape, and an edge of the tape being attached to the ring frame; a second holder configured to hold a second substrate, which is disposed on an opposite side to the tape with respect to the first substrate therebetween, while maintaining a distance from the first substrate; and a pressing device configured to press the multiple chips one by one with the tape therebetween to press and bond the corresponding chip to the second substrate.

A wafer bonding apparatus includes lower and upper stages, lower and upper push rods, a position detection sensor, and processing circuitry. The stages may vacuum suction respective wafers on respective surfaces of the stages based on a vacuum pressure being supplied to respective suction holes in the respective surfaces from a vacuum pump. The push rods are movable through respective center holes in the stages to apply pressure to respective middle regions of the respective wafers. The position detection sensor may generate information indicating a bonding propagation position of the wafers based on detecting at least one wafer through a detection hole in at least one stage. The processing circuitry may process the information to detect the bonding propagation position and cause a change of at least one of a ratio of protruding lengths of the push rods, or a ratio of suction areas of the stages.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.

According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.