A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

A method for the transfer of components from a sender substrate to a receiver substrate includes provision and/or production of the components on the sender substrate, transfer of the components of the sender substrate to the transfer substrate, and transfer of the components from the transfer substrate to the receiver substrate.The components can be transferred selectively by means of bonding means and/or debonding means.

A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

A die bonding system including a bond head assembly for bonding a die to a substrate is provided. The die includes a first plurality of fiducial markings, and the substrate includes a second plurality of fiducial markings. The die bonding system also includes an imaging system configured for simultaneously imaging one of the first plurality of fiducial markings and one of the second plurality of fiducial markings along a first optical path while the die is carried by the bond head assembly. The imaging system is also configured for simultaneously imaging another of the first plurality of fiducial markings and another of the second plurality of fiducial markings along a second optical path while the die is carried by the bond head assembly. Each of the first and second optical paths are independently configurable to image any area of the die including one of the first plurality of fiducial markings.

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.

A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.