Alignment of a first wafer bonded to a second wafer can be determined using electrical wafer alignment methods. A wafer stack can be formed by overlaying a second wafer over a first wafer such that second metal bonding pads of the second wafer contact first metal bonding pads of the first wafer. A leakage current or a capacitance measurement step is performed between first alignment diagnostic structures in the first wafer and second alignment diagnostic structures in the second wafer for multiple mating pairs of first semiconductor dies in the first wafer and second semiconductor dies in the second wafer to determine the alignment.

A method of fabricating a display device may include disposing a display panel on a stage to be parallel to an XZ-plane defined by a horizontal X-axis and a vertical Z-axis, measuring a height of a first side surface of the display panel in a direction of the Z-axis, rotating the stage such that the first side surface is parallel to a reference horizontal line in case that a result of the measured height indicates that the first side surface includes an inclined surface, moving the display panel in a direction of the Z-axis such that a first pad disposed on the first side surface overlaps the reference horizontal line, and bonding a second pad of a printed circuit board with the first pad.

A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

A bonding apparatus includes a first holder configured to hold a first substrate divided into multiple chips with a tape and a ring frame therebetween, the first substrate being attached to the tape, and an edge of the tape being attached to the ring frame; a second holder configured to hold a second substrate, which is disposed on an opposite side to the tape with respect to the first substrate therebetween, while maintaining a distance from the first substrate; and a pressing device configured to press the multiple chips one by one with the tape therebetween to press and bond the corresponding chip to the second substrate.

A wafer bonding apparatus includes lower and upper stages, lower and upper push rods, a position detection sensor, and processing circuitry. The stages may vacuum suction respective wafers on respective surfaces of the stages based on a vacuum pressure being supplied to respective suction holes in the respective surfaces from a vacuum pump. The push rods are movable through respective center holes in the stages to apply pressure to respective middle regions of the respective wafers. The position detection sensor may generate information indicating a bonding propagation position of the wafers based on detecting at least one wafer through a detection hole in at least one stage. The processing circuitry may process the information to detect the bonding propagation position and cause a change of at least one of a ratio of protruding lengths of the push rods, or a ratio of suction areas of the stages.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.

A method and apparatus for transferring components. A first substrate is provided with the components. A second substrate is provided with an adhesive layer comprising a hot melt adhesive material. The components on the first substrate are contacted with the adhesive layer on the second substrate while the adhesive layer is melted. The adhesive layer is allowed to solidify to form an adhesive connection between the components and the second substrate. The first and second substrates are moved apart to transfer the components. At least a subset of the components is transferred from the second substrate to a third substrate by radiating light onto the adhesive layer to form a jet of melted material carrying the components.

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.