A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

A chip package structure is provided. The chip package structure includes a wiring substrate having a pad and a conductive adhesive layer over the pad and having a first inner wall, a second inner wall, a first sidewall, and a second sidewall. The first inner wall and the second inner wall face each other, and the first sidewall and the second sidewall are opposite to each other. The chip package structure also includes a nickel layer over the conductive adhesive layer, and the nickel layer covers the first inner wall, the second inner wall, the first sidewall, and the second sidewall of the conductive adhesive layer. The chip package structure further includes a chip over the wiring substrate and a conductive bump connected between the nickel layer and the chip.

Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package.

In a method of manufacturing a display device, the method includes forming a first electrode on a substrate, forming an insulating layer over the first electrode, aligning a first light emitting element on the insulating layer, light-exposing the insulating layer, exposing at least a portion of the first electrode by developing the insulating layer, and bonding the first light emitting element to the at least a portion of the first electrode.

Disclosed are a semiconductor packaging method, a semiconductor component and an electronic device. The semiconductor packaging method comprises: forming first alignment bonding parts at first target positions on a carrier, and attaching interconnection devices to second target positions of the carrier, each of the interconnection devices having second alignment bonding parts formed on a side of the interconnection device facing away from the carrier. The method further comprises: aligning and connecting a portion of the third alignment bonding parts of an active surface of a respective semiconductor device with corresponding ones of the first alignment bonding parts, and aligning and connecting the remaining third alignment bonding parts of the active surface of the respective semiconductor device with corresponding ones of the second alignment bonding parts by fusion bonding. Bonding with the alignment bonding parts prevent the semiconductor device from shifting and rotating in a subsequent molding process, thereby improving the yield of the semiconductor packaging process.