A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.

A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 μm.

The present invention provides a highly reliable solder joint, the solder joint including a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface in contact with the solder joint layer, wherein the Ni—P—Cu plating layer contains Ni as a main component and contains 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, the Ni—P—Cu plating layer has a microcrystalline layer at an interface with the solder joint layer, and the microcrystalline layer includes a phase containing microcrystals of a NiCuP ternary alloy, a phase containing microcrystals of (Ni,Cu).sub.3P, and a phase containing microcrystals of Ni.sub.3P.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

Disclosed is a method of bonding two copper structures involving compressing a first copper structure with a second copper structure under a stress from 0.1 MPa to 50 MPa and under a temperature of 250 C. or less so that a bonding surface of the first copper structure is bonded to a bonding surface of the second copper structure; at least one of the bonding surface of the first copper structure and the bonding surface of the second copper structure have a layer of nanograins of copper having an average grain size of 5 nm to 500 nm, the layer of the nanograins of copper having a thickness of 10 nm to 10 m.

A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.

A semiconductor device according to an embodiment of the present invention comprises pads electrically connected to wires provided on an insulating substrate. A wiring substrate comprises a first insulant provided between the pads. A first semiconductor chip comprises metal bumps respectively connected to the pads on the wiring substrate on a first face facing the wiring substrate. A first adhesion layer is provided between the first insulant and the first semiconductor chip and adheres the wiring substrate and the first semiconductor chip to each other. An insulating resin is provided to cover peripheries of the first adhesion layer and the metal bumps between the wiring substrate and the first semiconductor chip, and a structure on the wiring substrate.

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

A method for assembling components includes assembling a first component including solder bumps with a second component including connectors. The assembly of the components is preceded by pre-treating the first and second components wherein the solder bumps are contacted with a pre-treatment liquid configured to at least partially remove an oxide layer initially present on the solder. The pre-treatment liquid is an aqueous solution containing carboxylic acids or polycarboxylic acids. The assembly of the components is carried out after the pre-treatment in the absence of liquid or gas flux.