H01L2224/81093

Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

NOVEL 3D INTEGRATION METHOD USING SOI SUBSTRATES AND STRUCTURES PRODUCED THEREBY

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Method and apparatus for chip-to-wafer integration

An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.