An input/output (I/O) circuit includes at least one I/O cell having a first size, and a high current circuit coupled to the at least one I/O cell. The high current circuit has a second size that is smaller than the first size. A connection bus is coupled to the high current circuit. The connection bus has the second size and is positioned in substantially a same location within the I/O circuit as the high current circuit. A bump or a bond pad is coupled to the connection bus.

A method, which includes: a first chip-position calculation step of taking an image of an upper surface of a reference chip and an image of a lower surface of a correction chip to calculate positions of the chips; a second chip-movement step of moving the reference chip to a position, based on a displacement amount between the chips that has been calculated based on the positions of the chips, at which a distance between the chips corresponds to a predetermined offset amount, and then placing the correction chip on the suction stage; a second chip-position calculation step of taking an image of an upper surface of the correction chip, and calculating a second position of the correction chip; and a correction amount calculation step of calculating a correction amount of the predetermined offset amount based on the position of the reference chip and the second position of the correction chip.

A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop.

Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.