An alignment method for aligning two substrates to be stacked, comprising measuring a position of a mark selected from plurality of marks disposed on at least one substrate of the two substrates and aligning the two substrates based on the position of the measured mark, wherein the mark to be measured is selected based on information relating to distortion of the at least one substrate. The mark may be a mark disposed in a region having a smaller distortion amount of the at least one substrate than a threshold. The mark may be a mark disposed in a region having a higher reproducibility of distortion that occurs in the at least one substrate than a threshold.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

A substrate bonding apparatus that bonds a first substrate and a second substrate together, comprising a joining section that joins the first substrate and second substrate together aligned to each other for stacking; a detecting section that detects an uneven state on at least one of the first substrate and second substrate prior to joining by the joining section; and a determining section that determines whether the uneven state detected by the detecting section satisfies a predetermined condition, wherein the joining section does not join the first substrate and the second substrate if it is determined by the determining section that the uneven state does not satisfy the predetermined condition.

A batch bonding apparatus and bonding method. The bonding apparatus comprises: a chip supply unit (10) for providing a chip (60) to be bonded; a substrate supply unit (20) for providing a substrate; a transfer unit (40) for transferring the chip (60) between the chip supply unit (10) and the substrate supply unit (20); and a pickup unit (30) disposed above the chip supply unit (10), for picking up the chip (60) from the chip supply unit (10) and uploading the chip (60) to the transfer unit (40) after flipping a marked surface of the chip (60) in a required direction. In the present invention pickup of each chip is completed individually, but transfer processes and bonding processes can be carried out for multiple chips at the same time, greatly increasing yield.

A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.

Semiconductor devices having measurement features and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a plurality of stacked semiconductor dies each having measurement features formed along an outer periphery of a surface thereof. One or more image capture devices can image the semiconductor device and a controller can detect the measurement features in imaging data received from the image capture devices. The controller can further determine the distance between two or more of the measurement features to estimate a bond line thickness between semiconductor dies in the stack.

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

A chip on glass package assembly includes a glass substrate, a first type chip, a second type chip and a plurality of connecting lines. The glass substrate includes an active area and a peripheral area connected to the active area. The first type chip is mounted on the peripheral area and including a processor. The second type chip is mounted on the peripheral area and located on a side of the first type chip, wherein the second type chip is different from the first type chip. The connecting lines are disposed on the peripheral area and connecting the first type chip and the second type chip.