A chip mounting system (1) includes: a chip supplying unit (11) for supplying a chip (CP); a stage (31) for holding a substrate (WT) in an orientation in which a mounting face (WTf) for mounting the chip (CP) faces vertically downward (Z direction); a head (33H) for holding the chip (CP) from the vertically downward direction (Z direction); and a head drive unit (36) for, by causing vertically upward (+Z direction) movement of the head (33H) holding the chip (CP), causes the head (33H) to approach the stage (31) to mount the chip (CP) on the mounting face (WTf) of the substrate (WT).

This semiconductor device is formed by stacking a plurality of semiconductor chips that each have a plurality of bump electrodes, each of the plurality of semiconductor chips being provided with an identification section formed on a respective side face. Each semiconductor chip has a similar arrangement for its respective plurality of bump electrodes, and each identification section is formed so that the positional relationship with a respective reference bump electrode provided at a specific location among the respective plurality of bump electrodes is the same in each semiconductor chip. The plurality of semiconductor chips are stacked such that the bump electrodes provided thereon are electrically connected in the order of stacking of the semiconductor chips, while the side faces on which the identification sections are formed are oriented in the same direction.

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

An integrated module includes a first component having a photonic device and electrical pads at a first side and a second side opposite to the first side, and a second component having electrical pads and bonded to the first component by matching their electrical pads. An optical signal is incident from an external medium to the photonic device through an anti-reflection coating at the second side of the first component, a partially-etched opening, or an etch-through opening. The opening can either be in the first component so the optical signal is incident at the photonic device from the second side or the opening can be in the second component so the optical signal is incident at the photonic device through part of the second component. When bonding the first component to the second component, a protrusion and indentation pair can be used to increase the alignment accuracy.

A batch bonding apparatus and bonding method. The bonding apparatus comprises: a chip supply unit (10) for providing a chip (60) to be bonded; a substrate supply unit (20) for providing a substrate; a transfer unit (40) for transferring the chip (60) between the chip supply unit (10) and the substrate supply unit (20); and a pickup unit (30) disposed above the chip supply unit (10), for picking up the chip (60) from the chip supply unit (10) and uploading the chip (60) to the transfer unit (40) after flipping a marked surface of the chip (60) in a required direction. In the present invention pickup of each chip is completed individually, but transfer processes and bonding processes can be carried out for multiple chips at the same time, greatly increasing yield.

The invention relates to the field of chip fabrication, in particular to the fabrication of superconducting integrated circuits for use in quantum computers. Raised and recessed alignment structures are provided on the surfaces of two substrate such that the raised and recessed alignment structure extends within the recessed alignment structure to a maximum depth determined by the geometry of the alignment structures. The alignment structures act as a hard stop for positioning and aligning the substrates for flip chip bonding.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

The invention concerns the calibration of a component mounting apparatus configured to mount components on a substrate whose mounting places do not contain local markings. The substrate contains either global substrate markings attached to its edge or other global features that can be used to mount the components. Calibration is carried out by means of a calibration plate which has several calibration positions distributed two-dimensionally over the calibration plate and provided with first optical markings, a test chip which has second optical markings, and a holder attached to the bonding station for temporarily accommodating the calibration plate. The number and arrangement of the calibration positions of the calibration plate and the number and arrangement of the mounting places of the substrate areapart from possible exceptionsdifferent from one another.

The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.

The system and method for a heterogeneous integrated circuit packaging method having an air-cavity lid to protect the active face of an integrated circuit, or other device, either active or passive, from the environment. The packaging is hermetic or near hermetic. In some examples, the cover provides electrical routing. In some examples, the cover also provides electromagnetic shielding. In some cases, an encapsulant and/or an overmoulding is provided to further protect the heterogeneous integrated circuit.